1. Field of the Invention
The present invention relates generally to a semiconductor nonvolatile memory device, and more particularly to a data sense circuit for reading out stored data.
2. Description of the Related Art
It is well known that, in an erasable programmable read-only memory, there is a concern that stored data in a memory cell is destroyed (or erroneously written) owing to a voltage stress at the time of data readout. When a given memory cell is selected, a power source potential Vcc is applied to a control gate and a drain of the selected memory cell. When the power source potential is repeatedly applied for a long time, electrons are injected in the floating gate of the memory cell gradually. In order to prevent such erroneous write, or so-called "soft write", the drain potential (column potential) of the memory cell at the time of readout is clamped to a value (e.g. 1.5 V) lower than the power source potential (normally 5 V), thereby enhancing the reliability of data retention by the memory cell. Structures of such a data sense circuit or its peripheral circuit for the EPROM are shown, for example, in 1984 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS, William Ip. Te-Long Chia et al., SESSION X: NONVOLATILE MEMORIES THAM 10.2: 256Kb CMOS EPROM, pp. 138, 139, FIG. 3(b); and 1985 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS, Saito et al., SESSION XII: NONVOLATILE MEMORIES THAM 13.8: A Programmable 80 ns 1Mb CMOS EPROM, pp. 176, 177, FIG. 2.
In data sense circuits disclosed in these documents, a current path of a transistor for clamping column potential is inserted between a column selection transistor and a power source, and also a current path of a transistor for a transfer gate is inserted between a column selection transistor and a sense line. A bias potential (e.g. 1.5 V) lower than a power source potential is applied to the gate of the column potential clamping transistor and to the gate of the transfer gate transistor. As a result, a drain potential of the memory cell at the time of readout is clamped to about 1.5 V lower than the power source potential.
In the above-described EPROM, when a data sense operation is carried out, data from the selected memory cell is amplified in two stages on the column line side and the sense line side separated by the transfer gate transistor. However, in the case of the two-stage sense system, if the level of data stored in the selected memory cell is low, the transfer gate transistor is located in a discharge path for discharging charge of the column line and the discharge speed is lowered owing to the resistance of the transfer gate transistor. Consequently, the access time increases.
The same problem resides in an electrically erasable programmable read-only memory (EEPROM) employing the two-stage sense system.